The invention relates to a memory cell configuration in which a plurality of memory cells are present in the region of a main area of a semiconductor substrate, in which the memory cells each contain at least one MOS transistor having a source, gate and drain, in which the memory cells are configured in memory cell rows which run essentially parallel, in which adjacent memory cell rows are insulated by an isolation trench, in which adjacent memory cell rows each contain at least one bit line, and where the bit lines of two adjacent memory cell rows face one another. The invention furthermore relates to a method for fabricating this memory cell configuration.
Memory cells are used in wide areas of technology. The memory cells may involve both read-only memories, which are referred to as ROMs, and programmable memories, which are referred to as PROMs (programmable ROMs).
Memory cell configurations on semiconductor substrates are distinguished by the fact that they allow random access to the information stored in them. They contain a multiplicity of transistors. During the reading operation, the logic states 1 or 0 are assigned to the presence or absence of a current flow through the transistor. The storage of the information is usually effected by using MOS transistors whose channel regions have a doping which corresponds to the desired blocking property.
A memory cell configuration of the generic type is shown in Yoshida (5,306,941). In this memory cell configuration, bit lines are configured in the edge region of memory cell webs, and the bit lines of adjacent memory cell webs face one another. In this case, the bit lines are isolated from one another in each case by an isolation trench filled with an insulating material. This document furthermore discloses a method for fabricating a memory cell configuration, in which memory cell webs are formed by etching isolation trenches into a semiconductor substrate. The etching of the isolation trenches is followed by diffusion of a dopant, bit lines being formed by the diffusion. This memory cell configuration of the generic type is suitable for feature sizes of at least 0.5 xcexcm and for a ROM read-only memory. Electrical programming is not possible in this case.
A further memory cell configuration is disclosed in DE 195 10 042 A1. This memory cell configuration contains MOS transistors configured in rows. The MOS transistors are connected in series in each row. In order to increase the storage density, adjacent rows are in each case configured alternately at the bottom of strip-type longitudinal trenches and between adjacent strip-type longitudinal trenches at the surface of the substrate. Interconnected source/drain regions are designed as a contiguously doped region. Row-by-row driving enables this memory cell configuration to be read.
This memory cell configuration is distinguished by the fact that the area requirement that is necessary for the memory cells has been reduced from 4 F2 to 2 F2 where F is the minimum feature size of the photolithographic process used for the fabrication. What is disadvantageous, however, is that a further increase in the number of memory cells per unit area is not possible in this case.
It is accordingly an object of the invention to provide a memory cell configuration and a method of producing the configuration which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type in such a way the greatest possible number of memory cells is configured in the smallest possible space. Preferably, the memory cell configuration shall also be electrically programmable.
In the case of a device of the generic type, this object is achieved by virtue of the fact that the isolation trench penetrates more deeply into the semiconductor substrate than the bit lines, and in that at least one partial region of the source and/or of the drain is situated underneath the isolation trench.
The invention thus provides for the memory cell configuration to be configured in such a way that it contains memory cell webs between which there are isolation trenches which penetrate deeply into the semiconductor substrate and thus enable effective insulation of mutually opposite bit lines.
An electrical connection between the sources and/or the drains of different memory cell webs is preferably effected by a partial region of the sources and/or of the drains extending from one memory cell web to a further memory cell well.
In this case, the sources and/or drains of different transistors are preferably located in a common well.
The memory cell configuration is made electrically programmable by the provision of a gate dielectric with traps for electrical charge carriers, for example a triple layer having a first SiO2 layer, layer, an Si3N4 layer and a second SiO2 layer, or the like.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration, that includes a semiconductor substrate with a plurality of memory cells each including at least one MOS transistor having a source, a gate, and a drain. The plurality of memory cells are configured in substantially parallel memory cell rows. Each of the memory cell rows include at least one bit line configured such that a bit line of one of the memory cell rows faces a bit line of an adjacent one of the memory cell rows. The semiconductor substrate includes isolation trenches insulating adjacent ones of the memory cell rows. The isolation trenches penetrate more deeply into the substrate than the at least one bit line. The at least one MOS transistor includes a region configured to be at least partially underneath the isolation trench, and the region is selected from the group consisting of the source and the drain.
In accordance with an added feature of the invention, the sources of adjacent ones of the MOS transistors are designed as a continuously doped region.
In accordance with an additional feature of the invention the drains of adjacent ones of the MOS transistors are designed as a continuously doped region.
In accordance with another feature of the invention, the isolation trenches penetrate from 0.1 xcexcm to 0.5 xcexcm more deeply into the semiconductor substrate than the at least one bit line.
In accordance with a further feature of the invention, the at least one bit line of each of the memory cell rows has a height of from 0.1 xcexcm to 0.3 xcexcm.
In accordance with a further added feature of the invention, there is provided a web with mutually opposite side walls configured between each two adjacent ones of the isolation trenches. Each web includes two of the memory cell rows. The at least one bit line of each of the memory cell rows adjoin one of the side walls of the web. Adjacent ones of the memory cells that are perpendicular to a course of the bit lines have a common region selected from the group consisting of a common source region and a common drain region.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for fabricating a memory cell configuration, which includes steps of: etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches; producing bit lines after channel regions have been produced; and subsequent to producing the bit lines, performing an etching step resulting in the isolation trenches penetrating more deeply into the semiconductor substrate.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration and method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.